1. Field of the Invention
This invention relates generally to the field of analog-to-digital converters and more particularly this invention relates to analog-to-digital converters which employ neural network and conventional analog-to-digital converter circuitry for converting an analog voltage into a digital signal.
1. Description of the Prior Art
A wide variety of electronic circuit designs for analog-to-digital converters (referred to hereinafter as A/D converters) are known in the art. One such design employs successive approximation to accomplish conversion. In this design a binary number generator is coupled to a digital-to-analog converter (hereinafter D/A converter). The output of the D/A converter is coupled to a first input of a comparator and the input analog voltage to be converted is coupled to a second input of the comparator. The output from the binary number generator changes in value until the output of the D/A converter approximately equals the input voltage. The binary number which the number generator is producing at the time the threshold is reached is considered the digital equivalent of the analog voltage. Although this circuit is not as complex as some other A/D converter designs, it must perform a series of approximations before an accurate result is achieved (n steps for an n-bit converter). Accordingly, this type of A/D converter is undesirably slow.
Another A/D converter which performs conversions faster than the successive approximation design is a parallel flash A/D converter. In a parallel flash A/D converter, a binary digital output representative of the analog input voltage is produced in a single clock cycle. Conventional flash A/D converters employ resistor ladder networks in which a series of resistors each having similar values are connected between a reference voltage and ground to form nodes between the resistors that provide reference voltages for a number of voltage comparators. The reference voltages are applied to a first input of each comparator and the analog input voltage to be converted is connected to a second input of the comparators. The output from the comparators depends on whether or not the input voltage exceeds the corresponding reference voltage. These outputs are encoded to produce a binary number having a value corresponding to the value of the analog input voltage. Although flash A/D converters are much faster than successive approximation designs, they require complex circuitry and have increased power requirements.
It is understood that in general there is a tradeoff between circuit size and speed in A/D converters. Conventional successive approximation A/D converters are smaller in size than flash converters, however, as noted, they require a relatively large number of clock cycles to provide an accurate digital representation of the input analog voltage. In contrast, the flash A/D converter produces an output in only a single clock cycle, however, the circuitry for this design is much more complex. This design requires a resistor ladder network having 2.sup.n +1 resistors for 2.sup.n stages, each of which includes a comparator in addition to the decoding network. Thus, this circuit requires a relatively large array of solid state devices for implementation.
Another approach to the design of analog to digital converters is found in U.S. Pat. No. 4,994,806 invented by Yun-Tae. This design improves conversion by combining both successive approximation and flash conversion for separate bits in the conversion process. This design provides conversion results more quickly than full successive approximation designs, however, it also requires a fairly large amount of circuitry and is not nearly as fast as the flash A/D converter.
U.S. Pat. No. 4,987,417 invented by Buckland discloses a final design which is an adaptive reference A/D converter. In this design, the outputs from higher-order comparators feed forward through a resistor network to the reference inputs of lower-order comparators. This forms a neural network for performing the conversion wherein the comparison voltage for a given comparator depends on the output of higher-order comparators. The conversion performed by this design is not complete, however, until each comparator produces a stable output. Additionally, the A/D converter neural network design of the Buckland Patent is of limited utility because the resistor network is difficult to implement in converter designs having higher resolution.
My co-pending United States patent application titled, Latched Neural Network A/D Converter, Ser. No. 08/255,085, filed Jun. 7, 1994 which is incorporated herein by reference, discloses improved neural network circuitry for use in A/D converters. Additionally, this application discloses circuitry which is capable of completing the conversion process in a limited number of neural network conversion steps.
While these designs have improved the speed of A/D converters and/or decreased the circuitry necessary for implementation, there remains a need in the field for fast A/D converters with high resolution and limited circuit complexity. It is therefore an object of the present invention to provide a high resolution, high speed A/D converter which performs the conversion with a limited number of circuit elements.